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| SL74LV573 OCTAL D-TYPE TRANSPARENT LATCH (3-State) By pinning SL74LV573 are compatible with SL74HC573 and SL74HCT573 series. Input voltage levels are compatible with stadard CMOS levels. * Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS * Voltage supply range from 1.2 to 5.5 V * LOW input current: 1.0 A; 0.1 A at O = 25 N * Output current 8 mA * Latch current: not less than150 mA at O = 125 N * ESD acceptable value: not less than 2000 V as per HBM and not less than 200 V as per MM ORDERING INFORMATION SL74LV573N Plastic DIP SL74LV573D SOIC TA = -40 to 125 C for all packages FUNCTION TABLE Inputs OE L L L H LE H H L X D H L X X Outputs Q H L no change Z PIN ASSIGNMENT OE D0 D1 D2 D3 D4 D5 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE H -HIGH voltage level L - LOW voltage level X - don't care Z - High impedance state D6 D7 GND SLS System Logic Semiconductor SL74LV573 ABSOLUTE MAXIMUM RATINGS Symbol Vcc Iik, Iok Io Icc IGND Tstg PD Parameter Supply voltage Input diode current Output diode current Output current bus drivers DC Vcc or GND current for types bus driver outputs GND current Storage temperature range Power dissipation per package: DIP SO Rating -0.5 to +7.0 20 50 35 70 50 -65 to +150 750 500 Unit V mA mA mA mA mA i Conditions VI<-0.5 V or VI>Vcc>+0.5 V V0<-0.5 V or VI>Vcc>+0.5 V -0.5 V mW Notes: Power dissipation value decreases for: DIP - 12 mWC the range from 70 to 125N SO - 8 mWC the range from 70 to 125N RECOMMENDED OPERATING CONDITIONS Symbol Vcc VI Vi T tr,tf Parameter Supply voltage Input voltage Output voltage Operating temperature range Input rise and fall times Min 1.0 0 0 -40 Max 5.5 Vcc Vcc +125 500 200 100 50 Unit V V V o Conditions C Vcc= 1.0 Vcc= 2.0 Vcc= 2.7 Vcc= 3.6 / 2.0 V / 2.7 V / 3.6 V / 5.5 V ns/V Note - The IC function down to Vnn = 1.0 V (input levels - VIL=0 V, VIH=Vcc); DC characterisics are guaranteed at Vcc=1.2 / 5.5 V. SLS System Logic Semiconductor SL74LV573 DC CHARACTERISTICS Sym bol Parameter Vcn (V) VIH HIGH level input voltage 1.2 2.0 2.7 to 3.6 4.5 to 5.5 1.2 2.0 2.7 to 3.6 4.5 to 5.5 1.2 2.0 2.7 3.6 5.5 3.0 4.5 VIH IO =-100 A or VIL Conditions VI -40 to +25C Min 0.9 1.4 2.0 0.7 Vcc 1.05 1.85 2.55 3.45 5.35 2.48 3.70 Max 0.3 0.6 0.8 0.3 Vcc Limits +85 iN Min 0.9 1.4 2.0 0.7 Vcc 1.0 1.8 2.5 3.4 5.3 2.40 3.60 Max 0.3 0.6 0.8 0.3 Vcc +125 iN Min 0.9 1.4 2.0 0.7 Vcc 1.0 1.8 2.5 3.4 5.3 2.20 3.50 Max -0.3 0.6 0.8 0.3 Vcc V Unit VIL LOW level output voltage V VOH HIGH level output voltage V VOH HIGH level output voltage; BUS driver outputs VOL LOW level output voltage VIH IO =-8 mA or IO =-16 mA VIL VIH IO =100A or VIL V 1.2 2.0 2.7 3.6 5.5 3.0 4.5 5.5 - 0.15 0.15 0.15 0.15 0.15 0.33 0.40 1.0 - 0.2 0.2 0.2 0.2 0.2 0.40 0.55 1.0 - 0.2 0.2 0.2 0.2 0.2 0.50 0.65 1.0 V VOL LOW level voltage; BUS driver outputs II Input leakage current OFF-state current Supply current Additional supply current per input VIH IO =8 mA or IO =16 mA VIL Vnn or GD N VIH or VIL Vnn Io = 0 or GD N V A IOZ 5.5 - 0.5 5.0 - 10.0 A Icc 5.5 8.0 80 160 A Icc 2.7 ai 3.6 VI = Vcc-0.6V - 0.2 0.5 - 0.85 mA SLS System Logic Semiconductor SL74LV573 AC CHARACTERISICS (CL=50 pF, RL=1 K, tLH = tHL = 2.5 ns) Sym bol Parameter Conditions Vcc -40 to +25C Min tPHL/PLH Propagation delay Dn to Qn 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.0 5.5 O=+25 iN O=+25 iN VI = Vcc or GND VI = Vcc or GND 100 29 21 17 15 50 15 11 8 6 40 8 8 8 8 Max 150 30 23 18 15 160 34 28 20 17 140 28 22 17 14 160 31 23 20 17 7.0 52 Limits +85C Min 125 34 25 20 18 75 17 13 10 8 40 8 8 8 8 Max 160 39 29 23 19 180 43 31 25 21 160 37 28 22 18 160 39 29 24 20 +125C Min 150 41 30 24 21 100 20 15 12 10 40 8 8 8 8 Max 170 49 36 29 24 190 53 34 31 26 170 48 35 28 23 170 48 36 29 24 ns Unit tPHL/PLH Propagation delay LE to Qn VI = Vcc or GND ns tPZH/PZL 3-state output enable time OE to Qn 3-state outpiut disable time OE to Qn LE pulse width HIGH VI = Vcc or GND ns tPHZ/PLZ VI = Vcc or GND ns tW ns tsu Setup time Dn to LE ns th Hold time Dn to LE ns CI CPD Input capacitance Power dissipation capacitance per package ns ns SLS System Logic Semiconductor SL74LV573 1.9 mm 18 19 20 17 16 15 14 13 12 On-chip marking 1.51 mm 11 74LV573/574 1 10 9 2 3 4 5 6 7 8 Drawing of the chip Pads allocation Table Pad number 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 coordinates (counted from lower left corner), mm Y X 0.128 0.545 0.128 0.229 0.330 0.120 0.576 0.120 0.738 0.120 1.054 0.120 1.216 0.120 1.466 0.120 1.682 0.314 1.682 0.533 1.682 0.839 1.682 1.108 1.422 1.274 1.149 1.274 0.971 1.274 0.811 1.274 0.633 1.274 System Logic Semiconductor Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 SLS SL74LV573 18 19 20 0.360 0.128 0.128 1.274 1.108 0.854 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 SLS System Logic Semiconductor |
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